%FILENAME%
vtr-9.0.0-1.1-x86_64_v4.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1.1

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
9133965

%ISIZE%
30417988

%SHA256SUM%
29ca44342b2cd599c3c38c4cb2515f16d08d9ba64110947f8e2023477cdb5cf0

%PGPSIG%
iQGzBAABCgAdFiEEiC3P5I4gUdSOJWKr87YHSI2zWkcFAmhOkS4ACgkQ87YHSI2zWkfPVAv/adS862GH89ORVoQEiPjlKo1icsRKI9uIVkuPblSaZ9m8rZ//ROe8sFrq80AHnClgRbE/7b559irDgs2S2Er/A2gL2HTJ7qUIjYLr/egXSoyvYJ7RqeR7P3o9xBc31RwGzF9CZjwjWi6ugJm4rpV9fIpBxnGzGNEBtKjrTmcdV2Tvwj9xfwlk7EXU+XbV5ggNxSaEEG2KoI9N1Nkcei8LH5jdNEaF1797+wSIZMvpFld+15mOBdWNrbeJ1kRRlAJHNz7ynDA1xzDdFO6+K2TGAQY1+tT+V25Av6agqAzLSqKLcrjyEhgj8v6wPJfRwI4lhL5TrgEx4cBvVMDf+dd10ioAnt7iK7AICt5c0NPHfwHiJbnVhFg9br0zApt/IRwzIYUq7BmZoCF54hValCylzRhU4SxD8Go0xsY0qpg5smR7zGm6HGLPs0Wtr/aNI11OBEaMl4TRYdISi7YbY9hZUH9A09Sa4UNmURRytmXXaolTHkyyXjTZS9+VdyuaJHcv

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64_v4

%BUILDDATE%
1749978992

%PACKAGER%
CachyOS <admin@cachyos.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

