%FILENAME%
vtr-9.0.0-1.2-x86_64_v4.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1.2

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
9185669

%ISIZE%
30331972

%SHA256SUM%
5c17eb2ffc629cb708aef5aad9a4958ecb7f09019974457d71ef4a09cfcd8ab9

%PGPSIG%
iQGzBAABCgAdFiEEiC3P5I4gUdSOJWKr87YHSI2zWkcFAmhPZ4MACgkQ87YHSI2zWkfksAwA7VbeGSymtxo4Q/JUaiPxO636xsroyLoB41HhHzD7YI8nlRZ6EYsw1ngRz+NnHchZd3tmazpMqODVwz/TnYt+HFRw8Uckvk0fAeEMpfcu7cC5wmViZIoXjv1X5j/4QTKVaBZLUVV0FWV16b8P77pthUhLVM3t14uuY7TLqf3kszQ6EqlSvXlwohVOT9Q2uKIQUEEYSp7Si0pG6th1hO734GGLM8v5bh+Ipqdj3+65GeMNBApOAgdCL6RB17l0QYNPx4n/i5VudADCrH2KGPX4L8QQ4y69xopjGuAkGp4XdwlAV93KGS3G2u3MjwQTHGK3HTIgQRv4wRTHyq7byQIx/y0Wmswqk66PqgOvGhCLpIxnfcXHgajk39dPYfb2xwpDh7i0E6qb84mVKORh+v20DKq9geBNX4aSjM9zqS85nb/NzlSJrWhVusbwfwu0s9Fk0TdrlaVDx6IruVc55h6KtCuwAo0puMJV7FLtdFPms5PK3JPIhgV40PIdC/R4IfsW

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64_v4

%BUILDDATE%
1750034076

%PACKAGER%
CachyOS <admin@cachyos.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

